CODE
The Hidden Language of Computer Hardware and Software

by Charles Petzold

-- Technical Addendum Version 0.90 --

Chapter 5, Page 38

It's possible to reduce to just one the number of wires in a bidirectional telegraph, but the reduction comes at a cost:

One Wire Telegraph

The downside of this circuit is that you and your friend canít send messages to each other simultaneously. To receive a message from your friend, the switch on your end must be depressed. Your friendís switch then turns both lights on and off. Similarly, when you want to send a message, your friendís switch must be depressed. If either switch is open, the light bulbs canít be lit. Because both light bulbs are always lit at the same time, twice as many batteries are needed; otherwise the bulbs would be a little dim. Because this configuration is more difficult to use than the two-wire version, itís probably not preferable even if it does save on wire.

Chapter 11, Page 113

There's actually a cheaper way to make a AND gate out of relays, requiring only one relay rather than two:

Alternate AND Gate

However, it's best if the output of relays is a full V. In this alternate configuration, if the top input is not a switch connected to V, the output may be less than V.

Chapter 12, Page 136

With the four gates from Chapter 11 (the AND, OR, NAND, and NOR) and the introduction of the XOR gate (and the mention of its complement, the equivalence gate) in this chapter, a total of six 2-input gates have been discussed. In theory, there are 16 different 2-input gates, as is shown in the table below. However, many of them are trivial or can be easily derived from the common gates:

A input: 0 0 1 1 Output Description
B input: 0 1 0 1
Output Bits
Gate 0: 0 0 0 0 Ground
Gate 1: 0 0 0 1 A AND B
Gate 2: 0 0 1 0 A AND NOT B
Gate 3: 0 0 1 1 A
Gate 4: 0 1 0 0 NOT A AND B
Gate 5: 0 1 0 1 B
Gate 6: 0 1 1 0 A XOR B
Gate 7: 0 1 1 1 A OR B
Gate 8: 1 0 0 0 A NOR B
Gate 9: 1 0 0 1 A EQU B
Gate 10: 1 0 1 0 NOT B
Gate 11: 1 0 1 1 A OR NOT B
Gate 12: 1 1 0 0 NOT A
Gate 13: 1 1 0 1 NOT A OR B
Gate 14: 1 1 1 0 A NAND B
Gate 15: 1 1 1 1 Voltage

Chapter 17, Page 214

The last paragraph on the page describes the control signals needed for the revised automated adder. What follows is a more extensive discussion of these control signals.

The eight bits of the output of the Code RAM array can be referred to as C0 (the least significant bit of the code), C1, C2, C3, C4, C5, C6, and C7 (the most significant bit):

Code RAM Output

Our job will be a little easier if we decode these signals for the operations they represent. For example, the output of this 8-input AND gate will be 1 if the operation code is a Halt:

Halt AND Gate

Similarly, this 8-input NOR gates can provide a signal called LOAD:

Load NOR Gate

Note the little circle on the C4 input that indicates that the signal is being inverted. Similar configurations can provide signals called STORE and ADD. And signals can be inverted like so:

Halt and Load Invert

As in the earlier circuit, a switch is attached to the clear inputs of the 16-bit counter and the 8-bit latch. But now Iím going to call this switch the Reset switch:

Reset Switch

An oscillator provides a Clock signal for the 16-bit counter and the latch, but now that Clock signal is 0 if the output of the Code RAM array is the Halt code:

Clock Signals

The inverse of the Clock signal is the Write input to the Data RAM array, but only if the operation is a Store:

Write Input to RAM

Finally, the Select input to the 2-Line-To-1-Line Data Selector should be 0 if the operation is Load and 1 otherwise:

Load Selector

And thatís it.

You begin using this automated adder by entering all the numbers and operations codes into the two RAM arrays. Letís assume you entered the values shown earlier. At the outset, the Reset switch is closed so the Reset signal in the timing diagram is 1. The counter output is 0000h, so the output of the Code RAM array is the value at the 0000h address, which is 10h. The output of the Data RAM array is the value 27h. The 10h output from the Code RAM array causes the select input to the 2-Line-To-1-Line Data Selector to be 0. The latch input is thus the output of the Data RAM array, which is 27h. The latch output is 00h because the clear signal (which is the Reset switch) is 1.

A timing diagram of some of this circuit might clarify how it works. When you open the Reset switch, things start moving:

Timing Diagram

At the next positive transition of the Clock signal after the Reset signal becomes 0, the latch output becomes 27h. The counter increments to 0001h. The output of the Code RAM array is 20h (the Add operation) and the output of the Data RAM array is A2h. The select input to the 2-Line-To-1-Line Data Selector is 1, which means that the input to the latch is the sum of the output of the Data RAM array (A2h) and the latch output (27h), or C9h.

At the next positive transition of the Clock signal, the counter increments to 0002h, and the latch output becomes C9h. The output of the Code RAM array is again 20h, and the output of the Data RAM array is the third number, 18h. The input to the latch is the sum of that value and the latch output, which is now C9h. That sum is E1h.

At the next positive transition of the clock signal, the counter increments to 0003h, and the latch output becomes E1h. The output of the Code RAM array is 11h, which is the code for the Store operation. The output of the Data RAM array is not important, which is why itís shown in the timing diagram as a blank. Nor is the input to the latch important. Whatís important is the output of the latch, which is connected to the data inputs of the Data RAM array. The RAM write signal writes that value into memory.

Similarly, the timing diagram also shows the second addition.

Chapter 17, Page 218

The following can be inserted following the table of operation codes:

I demonstrated earlier how 8-input AND gates or NOR gates can be wired up to produce signals that correspond to each opcode. For example:

Subtract With Borrow

Notice that C2, C3, C4, C6, and C7 are inverted before being inputs to the AND gate. The output of the 8-input AND gate will be 1 only if the operation code is 23h (Subtract with Borrow). Similarly, signals corresponding to the other operation codes can be generated. Adding the carry latch to implement these two new operation codes is a little messy but doesnít involve an inordinate amount of new components:

Carry Latch Circuit

Chapter 17, Page 222

The following can be inserted following the illustration:

As usual, the hard part is the little stuff--all those clocking signals and whatnot known collectively as the control signals. I wonít show the detailed control signals fpr this and future configurations. (Nor will I be sadistic enough to categorize this an ďexercise for the readerĒ!) But I will show you a very handy tool for generating complex control signals. This is known as a ring counter.

You may recall the edge-triggered D-type flip-flop with preset and clear that we encountered at the end of Chapter 14:

Edge-Triggered Flip-Flop

Normally, the Preset and Clear inputs are set to 0. Then, whenever the Clock input goes from 0 to 1, the Q output becomes the same as the Data input. When the Clear input is 1, then the Q output is 0, and when the Preset input is 1, then the Q output is 1:

InputsOutputs
PresetClearDClkQQ-bar
1 0 X X 1 0
0 1 X X 0 1
0 0 0 up-arrow 0 1
0 0 1 up-arrow 1 0
0 0 X 0 Q Q-bar

You can make a 4-bit ring counter by connecting four of these flip-flops like so:

Walking Ring Counter

Notice that a single Clock signal serves to clock all four flip-flops. Also notice that the Q output of each flip-flop is the D input of the next flip-flip. In fact, the Q output of the fourth flip-flip at the right is the D input of the first flip-flop at the right. A single Clear signal is connected to the Clear inputs of the first three flip-flops, and the Preset input of the fourth. Therefore, when the Clear signal is 1, then Q0, Q1, and Q2 are all 0 and Q3 is 1. When Clear goes to 0, then the Clock causes the outputs of the flip-flips to change as shown in the following timing diagram:

Walking Ring Timing Diagram

First Q0 is 1, then Q1 is 1, then Q2, then Q3, and back again to Q0.

Q0 can be used as the clock input of the top 8-bit latch--the one that holds the instruction code from the Code RAM. Q1 is the clock input of the middle 8-bit latch, which holds the high-order byte of the 16-bit address, and Q2 is the clock input of the bottom 8-bit latch, which holds the low-order byte of the 16-bit address. Q3 can be the clock input to the accumulator latch. During this time, the 16-bit counter needs to advance three times because each instruction is three bytes in length. The clock to the 16-bit counter can be:

Walking Ring Clock

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© Charles Petzold, 2000
code@charlespetzold.com
This page last updated January, 2000.